The present invention relates to microprocessors with two levels of cache, and in particular to those with a level two cache on-chip with a larger line size than the level one cache, and having inclusion.
With the high on-chip transistor integration technologies available today, modern microprocessor architectures are able to incorporate a small level one cache, typically broken up into a level one instruction cache and a level one data cache. This is typically backed up with a large level two cache which contains both instructions and data. Typically, the line size of a level one cache is much shorter, and is dictated by the number of address and data lines which can be internally routed on the chip and the machine architecture that demands tremendous level two cache bandwidth and minimum latency. In the level two cache, on the other hand, the line size is more dependent upon the external bus size or the size of a connection to a level three dedicated cache. An ideal line size for a level two cache might be up to four times or more longer than the level one cache line size for the optimal design conditions, considering the system bandwidth and the internal level one and level two cache bandwidth.
However, such a ratio of the level two to level one line size causes a problem in a multi-processor architecture where there is snooping on the level two cache. Snooping is done to maintain data consistency where multiple processors are operating on the same data. While a single snoop may go to a single line in a level two cache, this then requires multiple snoops to the level one cache. Even with a dual ported level one cache, such a number of snoops can interfere with the processor operation. Accordingly, typically designs keep the ratio of the level two line size to the level one line size to be two to one at the most.
It would be desirable to have a higher ratio of level two to level one cache line size, while reducing the number of snoops required.